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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad5330/ad5331/ad5340/ad5341 * one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 2000 2.5 v to 5.5 v, 115 a, parallel interface single voltage-output 8-/10-/12-bit dacs ad5330 functional block diagram (other diagrams inside) buffer 8-bit dac dac register input register inter- face logic power-down logic buf gain db 7 db 0 . . cs wr clr ldac v ref v dd v out pd gnd ad5330 power-on reset reset features ad5330: single 8-bit dac in 20-lead tssop ad5331: single 10-bit dac in 20-lead tssop ad5340: single 12-bit dac in 24-lead tssop ad5341: single 12-bit dac in 20-lead tssop low power operation: 115 a @ 3 v, 140 a @ 5 v power-down to 80 na @ 3 v, 200 na @ 5 v via pd pin 2.5 v to 5.5 v power supply double-buffered input logic guaranteed monotonic by design over all codes buffered/unbuffered reference input options output range: 0Cv ref or 0C2 v ref power-on reset to zero volts simultaneous update of dac outputs via ldac pin asynchronous clr facility low power parallel data interface on-chip rail-to-rail output buffer ampli?ers temperature range: C40 c to +105 c applications portable battery-powered instruments digital gain and offset adjustment programmable voltage and current sources programmable attenuators industrial process control general description the ad5330/ad5331/ad5340/ad5341 are single 8-, 10-, and 12-bit dacs. they operate from a 2.5 v to 5.5 v supply con- suming just 115 a at 3 v, and feature a power-down mode that further reduces the current to 80 na. these devices incorporate an on-chip output buffer that can drive the output to both supply rails, while the ad5330, ad5340, and ad5341 allow a choice of buffered or unbuffered reference input. the ad5330/ad5331/ad5340/ad5341 have a parallel inter face. cs selects the device and data is loaded into the input registers on the rising edge of wr . the gain pin allows the output range to be set at 0 v to v ref or 0 v to 2 v ref . input data to the dacs is double-buffered, allowing simultaneous update of multiple dacs in a system using the ldac pin. an asynchronous clr input is also provided, w hich resets the contents of the input register and the dac register to all zeros. these devices also incorporate a power-on reset circuit that ensures that the dac output powers on to 0 v and remains there until valid data is written to the device. the ad5330/ad5331/ad5340/ad5341 are available in thin shrink small outline packages (tssop). * protected by u.s. patent number 5,969,657; other patents pending.
rev. 0 C2C ad5330/ad5331/ad5340/ad5341?pecifications (v dd = 2.5 v to 5.5 v, v ref = 2 v. r l = 2 k to gnd; c l = 200 pf to gnd; all speci?ations t min to t max unless otherwise noted.) b version 2 parameter 1 min typ max unit conditions/comments dc performance 3, 4 ad5330 resolution 8 bits relative accuracy 0.15 1 lsb differential nonlinearity 0.02 0.25 lsb guaranteed monotonic by design over all codes ad5331 resolution 10 bits relative accuracy 0.5 4 lsb differential nonlinearity 0.05 0.5 lsb guaranteed monotonic by design over all codes ad5340/ad5341 resolution 12 bits relative accuracy 2 16 lsb differential nonlinearity 0.2 1 lsb guaranteed monotonic by design over all codes offset error 0.4 3 % of fsr gain error 0.15 1 % of fsr lower deadband 5 10 60 mv lower deadband exists only if offset error is negative upper deadband 10 60 mv v dd = 5 v. upper deadband exists only if v ref = v dd offset error drift 6 C12 ppm of fsr/ c gain error drift 6 C5 ppm of fsr/ c dc power supply rejection ratio 6 C60 db ? v dd = 10% dac reference input 6 v ref input range 1 v dd v buffered reference (ad5330, ad5340, and ad5341) 0.25 v dd v unbuffered reference v ref input impedance >10 m ? buffered reference (ad5330, ad5340, and ad5341) 180 k ? unbuffered reference. gain = 1, input impedance = r dac 90 k ? unbuffered reference. gain = 2, input impedance = r dac reference feedthrough C90 db frequency = 10 khz output characteristics 6 minimum output voltage 4, 7 0.001 v min rail-to-rail operation maximum output voltage 4, 7 v dd C0.001 v max dc output impedance 0.5 ? short circuit current 25 ma v dd = 5 v 15 ma v dd = 3 v power-up time 2.5 s coming out of power-down mode. v dd = 5 v 5 s coming out of power-down mode. v dd = 3 v logic inputs 6 input current 1 a v il , input low voltage 0.8 v v dd = 5 v 10% 0.6 v v dd = 3 v 10% 0.5 v v dd = 2.5 v v ih , input high voltage 2.4 v v dd = 5 v 10% 2.1 v v dd = 3 v 10% 2.0 v v dd = 2.5 v pin capacitance 3 pf power requirements v dd 2.5 5.5 v i dd (normal mode) dacs active and excluding load currents. unbuffered v dd = 4.5 v to 5.5 v 140 250 a reference. v ih = v dd , v il = gnd. v dd = 2.5 v to 3.6 v 115 200 ai dd increases by 50 a at v ref > v dd C 100 mv. in buffered mode extra current is (5 + v ref /r dac ) a, where r dac is the resistance of the resistor string. i dd (power-down mode) v dd = 4.5 v to 5.5 v 0.2 1 a v dd = 2.5 v to 3.6 v 0.08 1 a notes 1 see terminology section. 2 temperature range: b version: C40 c to +105 c; typical speci?cations are at 25 c. 3 linearity is tested using a reduced code range: ad5330 (code 8 to 255); ad5331 (code 28 to 1023); ad5340/ad5341 (code 115 to 40 95). 4 dc speci?cations tested with output unloaded. 5 this corresponds to x codes. x = deadband voltage/lsb size. 6 guaranteed by design and characterization, not production tested. 7 in order for the ampli?er output to reach its minimum voltage, offset error must be negative. in order for the ampli?er output to reach its maximum voltage, v ref = v dd and offset plus gain error must be positive. speci?cations subject to change without notice.
rev. 0 C3C ad5330/ad5331/ad5340/ad5341 ac characteristics 1 b version 3 parameter 2 min typ max unit conditions/comments output voltage settling time v ref = 2 v. see figure 20 ad5330 6 8 s 1/4 scale to 3/4 scale change (40 h to c0 h) ad5331 7 9 s 1/4 scale to 3/4 scale change (100 h to 300 h) ad5340 8 10 s 1/4 scale to 3/4 scale change (400 h to c00 h) ad5341 8 10 s 1/4 scale to 3/4 scale change (400 h to c00 h) slew rate 0.7 v/ s major code transition glitch energy 6 nv-s 1 lsb change around major carry digital feedthrough 0.5 nv-s multiplying bandwidth 200 khz v ref = 2 v 0.1 v p-p. unbuffered mode total harmonic distortion C70 db v ref = 2.5 v 0.1 v p-p. frequency = 10 khz notes 1 guaranteed by design and characterization, not production tested. 2 see terminology section. 3 temperature range: b version: C40 c to +105 c; typical speci?cations are at 25 c. speci?cations subject to change without notice. timing characteristics 1, 2, 3 parameter limit at t min , t max unit condition/comments t 1 0 ns min cs to wr setup time t 2 0 ns min cs to wr hold time t 3 20 ns min wr pulsewidth t 4 5 ns min data, gain, buf, hben setup time t 5 4.5 ns min data, gain, buf, hben hold time t 6 5 ns min synchronous mode. wr falling to ldac falling. t 7 5 ns min synchronous mode. ldac falling to wr rising. t 8 4.5 ns min synchronous mode. wr rising to ldac rising. t 9 5 ns min asynchronous mode. ldac rising to wr rising. t 10 4.5 ns min asynchronous mode. wr rising to ldac falling. t 11 20 ns min ldac pulsewidth t 12 20 ns min clr pulsewidth t 13 50 ns min time between wr cycles notes 1 guaranteed by design and characterization, not production tested. 2 all input signals are specified with tr = tf = 5 ns (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. 3 see figure 1. cs wr data, gain, buf, hben ldac 1 ldac 2 clr t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 notes: 1 synchronous ldac update mode 2 asynchronous ldac update mode figure 1. parallel interface timing diagram (v dd = 2.5 v to 5.5 v, all speci?ations t min to t max unless otherwise noted.) (v dd = 2.5 v to 5.5 v. r l = 2 k to gnd; c l = 200 pf to gnd; all speci?ations t min to t max unless otherwise noted.)
rev. 0 ad5330/ad5331/ad5340/ad5341 C4C caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad5330/ad5331/ad5340/ad5341 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings * (t a = 25 c unless otherwise noted) v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v digital input voltage to gnd . . . . . . . C0.3 v to v dd + 0.3 v digital output voltage to gnd . . . . . C0.3 v to v dd + 0.3 v reference input voltage to gnd . . . . C0.3 v to v dd + 0.3 v v out to gnd . . . . . . . . . . . . . . . . . . . C0.3 v to v dd + 0.3 v operating temperature range industrial (b version) . . . . . . . . . . . . . . . C40 c to +105 c storage temperature range . . . . . . . . . . . . C65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150 c tssop package power dissipation . . . . . . . . . . . . . . . (t j max C t a )/ ja mw ja thermal impedance (20-lead tssop) . . . . . 143 c/w ja thermal impedance (24-lead tssop) . . . . . 128 c/w ja thermal impedance (20-lead tssop) . . . . . . 45 c/w jc thermal impedance (24-lead tssop) . . . . . . 42 c/w reflow soldering peak temperature . . . . . . . . . . . . . . . . . . . . . 220 +5/C0 c time at peak temperature . . . . . . . . . . . . 10 sec to 40 sec * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this speci?cation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. ordering guide package model temperature range package description option ad5330bru C40 c to +105 c tssop (thin shrink small outline package) ru-20 ad5331bru C40 c to +105 c tssop (thin shrink small outline package) ru-20 ad5340bru C40 c to +105 c tssop (thin shrink small outline package) ru-24 ad5341bru C40 c to +105 c tssop (thin shrink small outline package) ru-20
rev. 0 ad5330/ad5331/ad5340/ad5341 C5C ad5330 functional block diagram buffer 8-bit dac dac register input register inter- face logic power-down logic buf gain db 7 db 0 . . cs wr clr ldac v ref v dd v out pd gnd ad5330 power-on reset reset ad5330 pin function descriptions pin no. mnemonic function 1 buf buffer control pin. this pin controls whether the reference input to the dac is buffered or unbuffered. 2 nc no connect. 3v ref reference input. 4v out output of dac. buffered output with rail-to-rail operation. 5 gnd ground reference point for all circuitry on the part. 6 cs active low chip select input. this is used in conjunction with wr to write data to the parallel interface. 7 wr active low write input. this is used in conjunction with cs to write data to the parallel interface. 8 gain gain control pin. this controls whether the output range from the dac is 0Cv ref or 0C2 v ref. 9 clr asynchronous active low control input that clears all input registers and dac registers to zero. 10 ldac active low control input that updates the dac registers with the contents of the input registers. 11 pd power-down pin. this active low control pin puts the dac into power-down mode. 12 v dd power supply input. these parts can operate from 2.5 v to 5.5 v and the supply should be decoupled with a 10 f capacitor in parallel with a 0.1 f capacitor to gnd. 13C20 db 0 Cdb 7 eight parallel data inputs. db 7 is the msb of these eight bits. ad5330 pin configuration top view (not to scale) 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 ad5330 ldac gain wr cs gnd buf v ref v out pd v dd db 0 db 1 db 2 db 3 db 4 db 5 db 6 db 7 8-bit clr nc = no connect nc
rev. 0 ad5330/ad5331/ad5340/ad5341 C6C ad5331 functional block diagram buffer 10-bit dac dac register input register inter- face logic power-down logic buf db 9 db 0 . . cs wr clr ldac v ref v dd v out pd gnd ad5331 reset power-on reset ad5331 pin function descriptions pin no. mnemonic function 1db 8 parallel data input. 2db 9 most significant bit of parallel data input. 3v ref unbuffered reference input. 4v out output of dac. buffered output with rail-to-rail operation. 5 gnd ground reference point for all circuitry on the part. 6 cs active low chip select input. this is used in conjunction with wr to write data to the parallel interface. 7 wr active low write input. this is used in conjunction with cs to write data to the parallel interface. 8 gain gain control pin. this controls whether the output range from the dac is 0Cv ref or 0C2 v ref . 9 clr active low control input that clears all input registers and dac registers to zero. 10 ldac active low control input that updates the dac registers with the contents of the input registers. 11 pd power-down pin. this active low control pin puts the dac into power-down mode. 12 v dd power supply input. these parts can operate from 2.5 v to 5.5 v and the supply should be decoupled with a 10 f capacitor in parallel with a 0.1 f capacitor to gnd. 13C20 db 0 Cdb 7 eight parallel data inputs. ad5331 pin configuration top view (not to scale) 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 ad5331 ldac gain wr cs gnd db 8 v ref v out pd v dd db 0 db 1 db 2 db 3 db 4 db 5 db 6 db 7 10-bit clr db 9
rev. 0 ad5330/ad5331/ad5340/ad5341 C7C ad5340 functional block diagram buffer 12-bit dac dac register input register inter- face logic power-down logic buf gain db 11 db 0 . . cs wr clr ldac v ref v dd v out pd gnd ad5340 power-on reset reset ad5340 pin function descriptions pin no. mnemonic function 1db 10 parallel data input. 2db 11 most significant bit of parallel data input. 3 buf buffer control pin. this pin co ntrols w hether the reference input to the dac is b uffered or unbuffered. 4v ref reference input. 5v out output of dac. buffered output with rail-to-rail operation. 6 nc no connect. 7 gnd ground reference point for all circuitry on the part. 8 cs active low chip select input. this is used in conjunction with wr to write data to the parallel interface. 9 wr active low write input. this is used in conjunction with cs to write data to the parallel interface. 10 gain gain control pin. this controls whether the output range from the dac is 0Cv ref or 0C2 v ref. 11 clr asynchronous active low control input that clears all input registers and dac registers to zero. 12 ldac active low control input that updates the dac registers with the contents of the input registers. 13 pd power-down pin. this active low control pin puts the dac into power-down mode. 14 v dd power supply input. these parts can operate from 2.5 v to 5.5 v and the supply should be decoupled with a 10 f capacitor in parallel with a 0.1 f capacitor to gnd. 15C24 db 0 Cdb 9 10 parallel data inputs. ad5340 pin configuration top view (not to scale) 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 ad5340 ldac gain wr cs db 10 v out gnd pd v dd db 0 db 1 db 2 db 7 db 6 db 3 db 4 db 5 12-bit v ref buf clr db 8 db 9 nc nc = no connect db 11
rev. 0 ad5330/ad5331/ad5340/ad5341 C8C ad5341 functional block diagram v out buffer 12-bit dac gnd ad5341 pd dac register low byte register v dd hben cs wr clr ldac reset power-on reset high byte register power-down logic buf gain db 7 db 0 . . inter- face logic v ref ad5341 pin function descriptions pin no. mnemonic function 1 hben high byte enable pin. this pin is used when writing to the device to determine if data is written to the high byte register or the low byte register. 2 buf buffer control pin. this pin controls whether the reference input to the dac is buffered or unbuffered. 3v ref reference input. 4v out output of dac. buffered output with rail-to-rail operation. 5 gnd ground reference point for all circuitry on the part. 6 cs active low chip select input. this is used in conjunction with wr to write data to the parallel interface. 7 wr active low write input. this is used in conjunction with cs to write data to the parallel interface. 8 gain gain control pin. this controls whether the output range from the dac is 0Cv ref or 0C2 v ref. 9 clr asynchronous active low control input that clears all input registers and dac registers to zero. 10 ldac active low control input that updates the dac registers with the contents of the input registers. 11 pd power-down pin. this active low control pin puts the dac into power-down mode. 12 v dd power supply input. these parts can operate from 2.5 v to 5.5 v and the supply should be decoupled with a 10 f capacitor in parallel with a 0.1 f capacitor to gnd. 13C20 db 0 Cdb 7 eight parallel data inputs. db 7 is the msb of these eight bits. ad5341 pin configuration top view (not to scale) 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 ad5341 ldac gain wr cs gnd v ref v out pd v dd db 0 db 1 db 2 db 3 db 4 db 5 db 6 db 7 12-bit clr hben buf
rev. 0 ad5330/ad5331/ad5340/ad5341 C9C terminology relative accuracy for the dac, relative accuracy or integral nonlinearity (inl) is a measure of the maximum deviation, in lsbs, from a straight line passing through the actual endpoints of the dac transfer function. typical inl versus code plot can be seen in figures 5, 6, and 7. differential nonlinearity differential nonlinearity (dnl) is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a speci?ed differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed mono- tonic by design. typical dnl versus code plot can be seen in figures 8, 9, and 10. gain error this is a measure of the span error of the dac (including any error in the gain of the buffer ampli?er). it is the deviation in slope of the actual dac transfer characteristic from the ideal expressed as a percentage of the full-scale range. this is illus- trated in figure 2. offset error this is a measure of the offset error of the dac and the output ampli?er. it is expressed as a percentage of the full-scale range. if the offset voltage is positive, the output voltage will still be positive at zero input code. this is shown in figure 3. because the dacs operate from a single supply, a negative offset cannot appear at the output of the buffer ampli?er. instead, there will be a code close to zero at which the ampli?er output saturates (ampli?er footroom). below this code there will be a deadband over which the output voltage will not change. this is illustrated in figure 4. output voltage dac code positive gain error actual ideal negative gain error figure 2. gain error output voltage dac code positive offset gain error and offset error actual ideal %
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output voltage dac code negative offset gain error and offset error actual ideal amplifier footroom (~1mv) negative offset deadband codes figure 4. negative offset error and gain error
rev. 0 ad5330/ad5331/ad5340/ad5341 C10C offset error drift this is a measure of the change in offset error with changes in temperature. it is expressed in (ppm of full-scale range)/ c. gain error drift this is a measure of the change in gain error with changes in temperature. it is expressed in (ppm of full-scale range)/ c. power-supply rejection ratio (psrr) this indicates how the output of the dac is affected by changes in the supply voltage. psrr is the ratio of the change in v out to a change in v dd for full-scale output of the dac. it is measured in dbs. v ref is held at 2 v and v dd is varied 10%. reference feedthrough this is the ratio of the amplitude of the signal at the dac output to the reference input when the dac output is not being up dated (i.e., ldac is high). it is expressed in dbs. major-code transition glitch energy major-code transition glitch energy is the energy of the impulse injected into the analog output when the dac changes state. it is normally speci?ed as the area of the glitch in nv secs and is measured when the digital code is changed by 1 lsb at the major carry transition (011 . . . 11 to 100 ...00 or 100...00 to 011 . . . 11). digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of the dac from the digital input pins of the device, but is measured when the dac is not being written to ( cs held high). it is speci?ed in nv secs and is measured with a full-scale change on the digital input pins, i.e., from all 0s to all 1s and vice versa. multiplying bandwidth the ampli?ers within the dac have a ?nite bandwidth. the multiplying bandwidth is a measure of this. a sine wave on the reference (with full-scale code loaded to the dac) appears on the output. the multiplying bandwidth is the frequency at which the output amplitude falls to 3 db below the input. total harmonic distortion this is the difference between an ideal sine wave and its attenuated version using the dac. the sine wave is used as the reference for the dac and the thd is a measure of the harmonics present on the dac output. it is measured in dbs.
rev. 0 ad5330/ad5331/ad5340/ad5341 C11C typical performance characteristics code inl error ?lsbs 1.0 0.5 ?.0 0 50 250 100 150 200 0 ?.5 t a = 25 c v dd = 5v figure 5. ad5330 typical inl plot code dnl error lsbs 0.3 0.3 0 50 250 100 150 200 0.1 0.2 0.2 0.1 0 t a = 25 c v dd = 5v figure 8. ad5330 typical dnl plot v ref v 1.00 1.00 0.25 0.00 0.75 0.50 error lsbs 2345 0.25 0.50 0.75 v dd = 5v t a = 25 c max inl max dnl min dnl min inl figure 11. ad5330 inl and dnl error vs. v ref code inl error lsbs 3 0 200 1000 400 600 800 0 1 2 3 2 1 t a = 25 c v dd = 5v figure 6. ad5331 typical inl plot code dnl error lsbs 0.6 0.4 0 200 1000 400 600 800 0.2 0.6 0.2 0 0.4 t a = 25 c v dd = 5v figure 9. ad5331 typical dnl plot temperature c error lsbs 1.00 0.75 1.00 40 0 120 40 80 0 0.25 0.50 0.75 0.50 0.25 v dd = 5v v ref = 3v max inl max dnl min dnl min inl figure 12. ad5330 inl error and dnl error vs. temperature code inl error lsbs 12 0 4 8 8 4 0 4000 1000 2000 3000 12 t a = 25 c v dd = 5v figure 7. ad5340 typical inl plot t a = 25 c v dd = 5v code dnl error lsbs 1.0 0.5 1.0 0 1000 4000 2000 3000 0 0.5 %
& +$)( !2' temperature c error % 40 0 120 40 80 0.0 0.5 1.0 1.0 0.5 v dd = 5v v ref = 2v gain error offset error figure 13. ad5330 offset error and gain error vs. temperature
rev. 0 ad5330/ad5331/ad5340/ad5341 C12C gain error v dd volts error % 0.2 0.6 01 3 0 0.4 t a = 25 c v ref = 2v 46 0.5 0.3 0.2 0.1 0.1 25 offset error figure 14. offset error and gain error vs. v dd v dd volts i dd a 300 200 0 3.0 5.0 3.5 4.0 4.5 100 t a = 25 c 2.5 5.5 figure 17. supply current vs. supply voltage ch1 1v , ch2 5v , time base = 5 s/div ch2 ch1 clk v out v dd = 5v t a = 25 c figure 20. half-scale settling (1/4 to 3/4 scale code change) 5v source sink/source current ma v out volts 5 0 01 3 4 46 1 2 3 25 3v source 3v sink 5v sink figure 15. v out source and sink current capability v dd volts i dd a 0.2 0 3.0 5.0 3.5 4.0 4.5 0.1 t a = 25 c 2.5 5.5 0.3 0.4 0.5 figure 18. power-down current vs. supply voltage v dd ch1 ch2 v out a t a = 25 c v dd = 5v v ref = 2v ch1 2v, ch2 200mv, time base = 200 s/div figure 21. power-on reset to 0 v dac code i dd a 300 250 0 zero-scale full-scale 200 150 100 50 v dd = 3.6v v dd = 5.5v t a = 25 c v ref = 2v %
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4 4 v logic volts i dd a 400 0 15 234 200 0 600 800 1000 1200 1400 1600 1800 t a = 25 c v dd = 3v v dd = 5v figure 19. supply current vs. logic input voltage ch1 500mv, ch2 5v, time base = 1 s/div ch1 ch2 t a = 25 c v dd = 5v v ref = 2v v out a pd r saa
rev. 0 ad5330/ad5331/ad5340/ad5341 C13C i dd a frequency 120 200 190 v dd = 5v v dd = 3v 180 170 160 150 140 130 110 100 90 80 figure 23. i dd histogram with v dd = 3 v and v dd = 5 v v ref volts full-scale error %fsr 0 2 34 5 0 0.2 0.4 1 v dd = 5v t a = 25 c 0.2 figure 26. full-scale error vs. v ref 250ns/div 0.903 0.904 0.905 0.906 0.907 0.908 0.909 0.910 0.911 0.912 0.913 0.914 0.915 0.916 0.917 figure 24. ad5340 major-code tran- sition glitch energy frequency khz 10 40 0.01 20 30 0 10 db 0.1 1 10 100 1k 10k 50 60 figure 25. multiplying bandwidth (small-signal frequency response) functional description the ad5330/ad5331/ad5340/ad5341 are single resisto r-string dacs fabricated on a cmos process with resolutions of 8, 10, 12, and 12 bits, respectively. they are written to using a parallel interface. they operate from single supplies of 2.5 v to 5.5 v and the output buffer amplifiers offer rail-to-rail output swing. the ad5330, ad5340, and ad5341 have a reference input that may be buffered to draw virtually no current from the reference source. the reference input of the ad5331 is unbuffered. the devices have a power-down feature that reduces current con- sumption to only 80 na @ 3 v. digital-to-analog section the architecture of one dac channel consists of a reference buffer and a resistor-string dac followed by an output buffer ampli?er. the voltage at the v ref pin provides the reference voltage for the dac. figure 27 shows a block diagram of the dac architecture. since the input coding to the dac is straight binary, the ideal output voltage is given by: vv d gain out ref n = 2 where: d = decimal equivalent of the binary code which is loaded to the dac register: 0C255 for ad5330 (8 bits) 0C1023 for ad5331 (10 bits) 0C4095 for ad5340/ad5341 (12 bits) n = dac resolution gain = output ampli?er gain (1 or 2) v out gain v ref buf dac register input register resistor string output buffer amplifier reference buffer figure 27. single dac channel architecture
rev. 0 ad5330/ad5331/ad5340/ad5341 C14C resistor string the resistor string section is shown in figure 28. it is simply a string of resistors, each of value r. the digital code loaded to the dac register determines at what node on the string the voltage is tapped off to be fed into the output ampli?er. the voltage is tapped off by closing one of the switches connecting the string to the ampli?er. because it is a string of resistors, it is guaranteed m onotonic. to output amplifier r r r r r v ref figure 28. resistor string dac reference input there is a reference input pin for the dac. the reference input is buffered on the ad5330/ad5340/ad5341 but can be config- ured as unbuffered also. the reference input of the ad5331 is unbuffered. the buffered/unbuffered option is controlled by the buf pin. in buffe red mode (buf = 1), the current drawn from an external reference voltage is virtually zero as the impedance is at least 10 m ? . the reference input range is 1 v to 5 v with a 5 v supply. in unbuffered mode (buf = 0), the user can have a reference voltage as low as 0.25 v and as high as v dd since there is no restriction due to headroom and footroom of the reference ampli- fier. the im pedance is still large at typically 180 k ? for 0Cv ref mode and 90 k ? for 0C2 v ref mode. if there is an external buffered reference (e.g., ref192) there is no need to use the on-chip buffer. output ampli?r the output buffer ampli?er is capable of generating output voltages to within 1 mv of either rail. its actual range depends on v ref , gain, the load on v out , and offset error. if a gain of 1 is selected (gain = 0), the output range is 0.001 v to v ref . if a gain of 2 is selected (gain = 1), the output range is 0.001 v to 2 v ref . however, because of clamping, the maximum output is limited to v dd C 0.001 v. the output ampli?er is capable of driving a load of 2 k ? to gnd or v dd , in parallel with 500 pf to gnd or v dd . the source and sink capabilities of the output ampli?er can be seen in figure 15. the slew rate is 0.7 v/ s with a half-scale settling time to 0.5 lsb (at eight bits) of 6 s with the output unloaded. see figure 20. parallel interface the ad5330, ad5331, and ad5340 load their data as a single 8-, 10-, or 12-bit word, while the ad5341 loads data as a low byte of eight bits and a high byte containing four bits. double-buffered interface the ad5330/ad5331/ad5340/ad5341 dacs all have double- buffered interfaces consisting of an input register and a dac register. dac data, buf, and gain inputs are written to the input register under control of the chip select ( cs ) and write ( wr ). access to the dac register is controlled by the ldac function. when ldac is high, the dac register is latched and the input register may change state without affecting the contents of the dac register. however, when ldac is brought low, the dac register becomes transparent and the contents of the input register are transferred to it. the gain and buffer control signals are also double-buffered and are only updated when ldac is taken low. double-buffering is also useful where the dac data is loaded in two bytes, as in the ad5341, because it allows the whole data word to be assembled in parallel before updating the dac register. this prevents spurious outputs that could occur if the dac register were updated with only the high byte or the low byte. these parts contain an extra feature whereby the dac regis- ter is not updated unless its input register has been updated since the last time that ldac was brought low. normally, when ldac is brought low, the dac register is filled with the contents of the input register. in the case of the ad5330/ad5331/ ad5340/ad5341, the part will only update the dac register if the input register has been chan ged since the last time the dac register was updated. this removes unnecessary crosstalk. clear input ( clr ) clr is an active low, asynchronous clear that resets the input and dac registers. chip select input ( cs ) cs is an active low input that selects the device. write input ( wr ) wr is an active low input that controls writing of data to the device. data is latched into the input register on the rising edge of wr . load dac input ( ldac ) ldac transfers data from the input register to the dac register (and hence updates the outputs). use of the ldac function en ables double-buffering of the dac data, gain, and buf. there are two ldac modes: synchronous mode : in this mode the dac register is updated after new data is read in on the rising edge of the wr input. ldac can be tied permanently low or pulsed as in figure 1. asynchronous mode : in this mode the outputs are not up dated at the same time that the input register is written to. when ldac goes low, the dac register is updated with the contents of the input register. high-byte enable input (hben) high-byte enable is a control input on the ad5341 only that determines if data is written to the high-byte input register or the low-byte input register.
rev. 0 ad5330/ad5331/ad5340/ad5341 C15C the low data byte of the ad5341 consists of data bits 0 to 7 at data inputs db 0 to db 7 , while the high byte consists of data bits 8 to 11 at data inputs db 0 to db 3 as shown in figure 29. db 4 to db 7 are ignored during a high-byte write, but they may be used for data to set up the reference input as buffered/ unbuffered, and buffer amplifier gain. see figure 33. db8 db9 x x high byte low byte x = unused bit db0 db1 db2 db3 db4 db5 db6 db7 xx db10 db11 figure 29. data format for ad5341 power-on reset the ad5330/ad5331/ad5340/ad5341 are provided with a power-on reset function, so that they power up in a de?ned state. the power-on state is: ? normal operation ? reference input unbuffered ?0 C v ref output range ? output voltage set to 0 v both input and dac registers are ?lled with zeros and remain so until a valid write sequence is made to the device. this is particularly useful in applications where it is important to know the state of the dac outputs while the device is powering up. power-down mode the ad5330/ad5331/a d5340/ad5341 have low power con- sumption, dissipating only 0.35 mw with a 3 v supply and 0.7 mw with a 5 v supply. power consumption can be fur ther reduced when the dac is not in use by putting it into power- down mode, which is selected by taking pin pd low. when the pd pin is high, the dac works normally with a typical power consumption of 140 a at 5 v (115 a at 3 v). in power-down mode, however, the supply current falls to 200 na at 5 v (80 na at 3 v) when the dac is powered-down. not only does the supply current drop, but the output stage is also inter nally switched from the output of the amplifier mak- ing it open-ci rcuit. this has the advantage that the output is three-state while the part is in power-down mode and pro- vides a defined input condition for whatever is connected to the output of the dac amplifier. the output stage is illus- trated in figure 30. resistor string dac power-down circuitry amplifier v out figure 30. output stage during power-down the bias generator, the output ampli?er, the resistor string, and all other associated linear circuitry are shut down when the power-down mode is activated. however, the contents of the registers are unaffected when in power-down. the time to exit pow er-down is typically 2.5 s for v dd = 5 v and 5 s when v dd = 3 v. this is the time from a rising edge on the pd pin to when the output voltage deviates from its power- down voltage. see figure 22. table i. ad5330/ad5331/ad5340 truth table clr ldac cs wr function 111xno d ata transfer 1 1 x 1 no data transfer 0 xxxc lear all registers 1100 ? 1 load input register 1000 ? 1 load input register and dac register 1 0 x x update dac register x = dont care. table ii. ad5341 truth table clr ldac cs wr hben function 1 1 1 x x no data transfer 1 1 x 1 x no data transfer 0 xxxxc lear all registers 1100 ? 1 0 load low-byte input register 1100 ? 1 1 load high-byte input register 1000 ? 1 0 load low-byte input register and dac r egister 1000 ? 1 1 load high-byte input register and dac r egister 1 0 xxxu pdate dac register x = dont care.
rev. 0 ad5330/ad5331/ad5340/ad5341 C16C suggested databus formats in most applications gain and buf are hard-wired. however, if more flexibility is required, they can be included in a databus. this enables you to software program gain, giving the option of doubling the resolution in the lower half of the dac range. in a bused system, gain and buf may be treated as data inputs since they are written to the device during a write operation and take effect when ldac is taken low. this means that the refer- ence buffers and the output amplifier gain of multiple dac devices can be controlled using common gain and buf lines. in the case of the ad5330 this means that the databus must be wider than eight bits. the ad5331 and ad5340 databuses must be at least 10 and 12 bits wide respectively and are best suited to a 16-bit databus system. examples of data formats for putting gain and buf on a 16- bit databus are shown in figure 31. note that any unused bits above the actual dac data may be used for buf and gain. dac devices can be controlled using common gain and buf lines. ad5331 db0 db1 db2 db3 db4 db5 db6 db7 gain x x x x buf xx ad5330 ad5340 x = unused bit db0 db1 db2 db3 db4 db5 db6 db7 gain x x buf x x db9 db8 db0 db1 db2 db3 db4 db5 db6 db7 gain buf x x db9 db8 db10 db11 figure 31. gain and buf data on a 16-bit bus the ad5341 is a 12-bit device that uses byte load, so only four bits of the high byte are actually used as data. two of the unused bits can be used for gain and buf data by connecting them to the gain and buf inputs; e.g., bits 6 and 7, as shown in figures 32 and 33. data inputs buf gain ldac clr cs wr hben ad5341 db 7 db 6 8-bit data bus figure 32. ad5341 data format for byte load with gain and buf data on 8-bit bus in this case, the low byte is written first in a write operation with hben = 0. bits 6 and 7 of dac data will be written into gain and buf registers but will have no effect. the high byte is then w ritten. only the lower four bits of data are written into the dac h igh byte register, so bits 6 and 7 can be gain and buf data. ldac is used to update the dac, gain and buf values. db8 db9 high byte low byte x = unused bit db0 db1 db2 db3 db4 db5 db6 db7 x x db10 db11 buf gain figure 33. ad5341 with gain and buf data on 8-bit bus applications information typical application circuits the ad5330/ad5331/ad5340/ad5341 can be used with a wide range of reference voltages, especially if the reference inputs are configured to be unbuffered, in which case the devices offer full, one-quadrant multiplying capability over a reference r ange of 0.25 v to v dd . more typically, these devices may be used with a fixed, precision reference voltage. figure 34 shows a typical setup for the devices when using an external reference connected to the unbuffered reference inputs. if the reference inputs are unbuf- fered, the reference input range is from 0.25 v to v dd , but if the on-chip reference buffers are used, the reference range is reduced. suitable references for 5 v operation are the ad780 and ref192. for 2.5 v operation, a suitable external reference would be the ad589, a 1.23 v bandgap reference. ad5330/ad5331/ ad5340/ad5341 v out 0.1 f v dd = 2.5v to 5.5v v dd gnd ad780/ref192 with v dd = 5v or ad589 with v dd = 2.5v v ref gnd v out v in ext ref 10 f figure 34. ad5330/ad5331/ad5340/ad5341 using external reference driving v dd from the reference voltage if an output range of zero to v dd is required, the simplest solu- tion is to connect the reference inputs to v dd . as this supply may not be very accurate, and may be noisy, the devices may be powered from the reference voltage, for example u sing a 5 v reference such as the adm663 or adm666, as shown in figure 35. ad5330/ad5331/ ad5340/ad5341 v out v dd gnd v ref gnd v out(2) v in adm663/adm666 vset shdn sense 6v to 16v 0.1 f 10 f 0.1 f figure 35. using an adm663/adm666 as power and refer- ence to ad5330/ad5331/ad5340/ad5341
rev. 0 ad5330/ad5331/ad5340/ad5341 C17C bipolar operation using the ad5330/ad5331/ad5340/ad5341 the ad5330/ad5331/ad5340/ad5341 have been designed for single supply operation, but bipolar operation is achievable using the circuit shown in figure 36. the circuit shown has been con?gured to achieve an output voltage range of C5 v < v o < +5 v. rail-to-rail operation at the ampli?er output is achievable using an ad820 or op295 as the output ampli?er. the output voltage for any input code can be calculated as follows: v o = [(1 + r 4/ r 3) ( r 2/( r 1 + r 2) (2 v ref d / 2 n )] C r 4 v ref / r 3 where: d is the decimal equivalent of the code loaded to the dac, n is dac resolution and v ref is the reference voltage input. with: v ref = 2.5 v r1 = r3 = 10 k ? r2 = r4 = 20 k ? and v dd = 5 v. v out = (10 d/2 n ) C 5 ad5330/ad5331/ ad5340/ad5341 gnd v dd = 5v ext ref v out ad780/ref192 with v dd = 5v or ad589 with v dd = 2.5v gnd v in v out v ref v dd r3 10k r1 10k r2 20k r4 20k 5v +5v 5v 0.1 f 0.1 f 10 f figure 36. bipolar operation using the ad5330/ad5331/ ad5340/ad5341 decoding multiple ad5330/ad5331/ad5340/ad5341 the cs pin on these devices can be used in applications to decode a number of dacs. in this application, all dacs in the system receive the same data and wr pulses, but only the cs to one of the dacs will be active at any one time, so data will only be written to the dac whose cs is low. if multiple ad5341s are being used, a common hben line will also be required to determine if the data is written to the high-byte or low-byte register of the selected dac. the 74hc139 is used as a 2- to 4-line decoder to address any of the dacs in the system. to prevent timing errors, the enable input should be brought to its inactive state while the coded address inputs are changing state. figure 37 shows a d iagram of a typical setup for decoding multiple devices in a system. once data has been written sequentially to all dacs in a system, all the dacs can be updated simultaneously using a common ldac line. a common clr line can also be used to reset all dac outputs to zero. enable coded address 1g 1a 1b v dd v cc 74hc139 dgnd 1y0 1y1 1y2 1y3 hben wr ldac clr data inputs data inputs data inputs data inputs data bus *ad5341 only hben* wr ldac clr cs ad5330/ad5331/ ad5340/ad5341 hben* wr ldac clr cs hben* wr ldac clr cs hben* wr ldac clr cs ad5330/ad5331/ ad5340/ad5341 ad5330/ad5331/ ad5340/ad5341 ad5330/ad5331/ ad5340/ad5341 figure 37. decoding multiple dac devices
rev. 0 ad5330/ad5331/ad5340/ad5341 C18C programmable current source figure 38 shows the ad5330/ad5331/ad5340/ad5341 used as the control element of a programmable current source. in this example, the full-scale current is set to 1 ma. the output volt- age from the dac is applied across the current setting resistor of 4.7 k ? in series with the 470 ? adjustment potentiometer, which gives an adjustment of about 5%. suitable transistors to place in the feedback loop of the amplifier include the bc107 and the 2n3904, which enable the current source to operate from a minimum v source of 6 v. the operating range is deter- mined by the operating characteristics of the transistor. suitable amplifiers include the ad820 and the op295, both having rail- to-rail o peration on their outputs. the current for any digital input code and resistor value can be calculated as follows: igv d r ma ref n = () 2 where: g is the gain of the buffer ampli?er (1 or 2) d is the digital equivalent of the digital input code n is the dac resolution (8, 10, or 12 bits) r is the sum of the resistor plus adjustment potentiometer in k ? ad5330/ad5331/ ad5340/ad5341 gnd v dd = 5v ext ref v out ad780/ref192 with v dd = 5v gnd v in v out v ref v dd 4.7k 5v 0.1 f 0.1 f 10 f 470 load v source ad820/ op295 figure 38. programmable current source power supply bypassing and grounding in any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board on which the ad5330/ad5331/ad5340/ad5341 is mounted should be designed so that the analog and digital sections are separated, and con?ned to certain areas of the board. if the device is in a system where multiple devices require an agnd-to-dgnd connection, the connection should be made at one point only. the star ground point should be established as closely as pos- sible to the device. the ad5330/ad5331/ad5340/ad5341 should have ample supply bypassing of 10 f in parallel with 0.1 f on the supply located as close to the package as pos- sible, ideally right up against the device. the 10 f capacitors are the ta ntalum bead type. the 0.1 f capacitor should have low effective series resistance (esr) and effective series induc- tance (esi), like the common ceramic types that provide a low impedance path to ground at high frequencies to handle tran- sient currents due to internal logic switching. the power supply lines of the device should use as large a trace as possible to provide low impedance paths and reduce the ef fects of glitches on the power supply line. fast switching signals such as clocks should be shielded with digital ground to avoid radiat- ing noise to other parts of the board, and should never be run near the reference inputs. avoid crossover of digital and ana- log signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feed- through through the board. a microstrip technique is by far the best, but not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the solder side.
rev. 0 ad5330/ad5331/ad5340/ad5341 C19C table iii. overview of ad53xx parallel devices part no. resolution dnl v ref pins settling time additional pin functions package pins singles buf gain hben clr ad5330 8 0.25 1 6 s tssop 20 ad5331 10 0.5 1 7 s tssop 20 ad5340 12 1.0 1 8 s tssop 24 ad5341 12 1.0 1 8 s tssop 20 duals ad5332 8 0.25 2 6 s tssop 20 ad5333 10 0.5 2 7 s tssop 24 ad5342 12 1.0 2 8 s tssop 28 ad5343 12 1.0 1 8 s tssop 20 quads ad5334 8 0.25 2 6 s tssop 24 ad5335 10 0.5 2 7 s tssop 24 ad5336 10 0.5 4 7 s tssop 28 AD5344 12 1.0 4 8 s tssop 28 table iv. overview of ad53xx serial devices part no. resolution no. of dacs dnl interface settling time package pins singles ad5300 8 1 0.25 spi 4 s sot-23, microsoic 6, 8 ad5310 10 1 0.5 spi 6 s sot-23, microsoic 6, 8 ad5320 12 1 1.0 spi 8 s sot-23, microsoic 6, 8 ad5301 8 1 0.25 2-wire 6 s sot-23, microsoic 6, 8 ad5311 10 1 0.5 2-wire 7 s sot-23, microsoic 6, 8 ad5321 12 1 1.0 2-wire 8 s sot-23, microsoic 6, 8 duals ad5302 8 2 0.25 spi 6 s microsoic 8 ad5312 10 2 0.5 spi 7 s microsoic 8 ad5322 12 2 1.0 spi 8 s microsoic 8 ad5303 8 2 0.25 spi 6 s tssop 16 ad5313 10 2 0.5 spi 7 s tssop 16 ad5323 12 2 1.0 spi 8 s tssop 16 quads ad5304 8 4 0.25 spi 6 s microsoic 10 ad5314 10 4 0.5 spi 7 s microsoic 10 ad5324 12 4 1.0 spi 8 s microsoic 10 ad5305 8 4 0.25 2-wire 6 s microsoic 10 ad5315 10 4 0.5 2-wire 7 s microsoic 10 ad5325 12 4 1.0 2-wire 8 s microsoic 10 ad5306 8 4 0.25 2-wire 6 s tssop 16 ad5316 10 4 0.5 2-wire 7 s tssop 16 ad5326 12 4 1.0 2-wire 8 s tssop 16 ad5307 8 4 0.25 spi 6 s tssop 16 ad5317 10 4 0.5 spi 7 s tssop 16 ad5327 12 4 1.0 spi 8 s tssop 16 visit our web-page at http://www.analog.com/support/standard_linear/selection_guides/ad53xx.html
rev. 0 C20C c3828C2.5C4/00 (rev. 0) printed in u.s.a. ad5330/ad5331/ad5340/ad5341 outline dimensions dimensions shown in inches and (mm). 20-lead thin shrink small outline package tssop (ru-20) 20 11 10 1 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 0.260 (6.60) 0.252 (6.40) seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0 24-lead thin shrink small outline package tssop (ru-24) 24 13 12 1 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 0.311 (7.90) 0.303 (7.70) seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0

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